Digital devices are prevalent nowadays. While spreading, exchanging, and processing digital information using digital devices, it is necessary to operate in coordination with clocks in circuits for processing digital signals or even the data attached in digital signals. For example, the central processing unit (CPU) in computer architecture should operate in coordination with the clock signal for driving the various digital circuits inside the CPU to operate in coordination with the clock signal for accessing data, processing data, or controlling hardware. In addition, in mobile devices, it is also required to use clocks for triggering transmission of digital information; synchronization in clocks is required before correct data access between digital devices. In the process of clock synchronization described above, the adopted technologies can be categorized into frequency division and frequency multiplication for giving, though different frequencies, harmonic and synchronized clocks, which would facilitate coordination of digital data processing among different digital circuits.
In order to accelerate extraction of digital data, digital devices need to use the positive and negative edges of clock signals, which require the duty cycle of the clock signals to be 50%. Nonetheless, owing to imbalanced charge and discharge time via transistors and variations in process, temperature, and operating voltage, the duty cycle of clock signals in digital devices is not equal to 50%. Thereby, it is not possible to adopt the positive and negative edges of clock signals for accelerating digital data extraction. Besides, errors may occur during data acquisition. For solving the problems described above, it is required to use a correction circuit for duty cycle to change the pulse width so that the duty cycle of the clock signals can recover to 50%.
As compared to an analog duty-cycle corrector (DCC), a full-digital DCC does not use the voltage control method, and thus it is less influenced by the leakage current of transistors especially in advanced CMOS processes. In addition, the all-digital DCC owns the advantages of fast lock-in time and has a wide range of duty cycle correction. Thereby, general semiconductor digital devices, for example, memory devices, use extensively digital DCC to correct the duty cycle of clock signals. The digital DCC according to the prior art adopts a time to digital converter (TDC) to quantize the period of the reference clock and then generates a half-cycle delay signal via a delay circuit for generating a clock signal with 50% duty cycle. Nevertheless, while adopting the time to digital converter architecture with a wide range of clock frequency, because the TDC accuracy has to be maintained and the operating frequency has to be wide, the overall circuit area occupied by the digital DCC will increase significantly.
Furthermore, by using the TDC architecture, the half-cycle delay circuit has to be included, which makes the tuning accuracy of the digital DCC become twice the accuracy of the TDC, and hence limiting the accuracy of the digital DCC and resulting in excessive error in duty cycle.
Accordingly, the present invention provides a full-digital clock correction circuit and a method thereof, which improve the problems using the TDC architecture according to the prior art. In addition, the accuracy in clock duty cycle correction is improved, and the frequency range and the duty cycle range of the supported clock signals are widened as well.